Generally, a semiconductor memory device such as DRAM (Dynamic Random Access Memory) may be tested with a lot of test benches to detect faults of circuits at both the wafer level and package level. Because, in a practical sense, test coverage of a semiconductor memory device cannot be 100%, a semiconductor memory device that passes a test may still generate errors during user operation.
When the semiconductor memory device is attached to a printed circuit board (PCB), an error of the semiconductor memory device may be found based on a dump result of signals on pins connecting the semiconductor memory device and the PCB. The dump result may be obtained by a logic analyzer through connecting probes of the logic analyzer to the pins.
Mobile DRAM included in recently developed embedded systems may be mounted on an SoC (System-on-Chip) in PoP (Package on Package) form and the SoC may be mounted on the PCB of the embedded system. In this case, because internal pins connecting the mobile DRAM and the SoC are not exposed to the outside, it may be impossible to observe signals on the internal pins through the logic analyzer such that it may be difficult to detect certain errors of the embedded system.